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asahi kasei [AK4353] ms0016-e-01 2000/07 - 1 - general description the AK4353 is a stereo cmos d/a converter and digital audio interface transmitter. the dac signal outputs are single-ended and are analog filtered to remove out of band noise. therefore no external filters are required. the AK4353 can operate at the power supply from 2.7v to 5.5v and the digital i/f can correspond to both ttl and cmos levels. features o stereo ds dac o s/(n+d): 90db@5v o dr: 102db@5v o s/n: 102db@5v o sampling speed: 16khz ~ 96khz o multiple master clock frequencies: 256fs/384fs/512fs/768fs/1024fs/1536fs for half speed (16khz ~ 24khz) 256fs/384fs/512fs/768fs for normal speed (32khz ~ 48khz) 128fs/192fs/256fs/384fs for double speed (64khz ~ 96khz) o data input formats: lsb justified / msb justified / i 2 s selectable o selectable function: soft mute digital attenuator (256 steps) digital de-emphasis (44.1khz/48khz/32khz) o output mode: stereo, mono, reverse, mute o on-chip digital audio interface transmitter: compatible with s/pdif, iec958, aes/ebu & eiaj cp1201 consumer mode o input level: ttl/cmos selectable o output level: 3.0vpp@5v o control mode: 3-wire serial / i 2 c bus o low power dissipation: 80mw@5v o small 24pin vsop package o power supply: 2.7 ~ 5.5v o ta: -40 ~ 85 c 96khz 24bit ds dac with dit AK4353
asahi kasei [AK4353] ms0016-e-01 2000/07 - 2 - n block diagram ds modulator mcko lrck aoutl pdn dvdd dvss 8x interpolator clock generator lpf ds modulator aoutr 8x interpolator lpf bick sdti serial input interface mcki avdd avss vcom cclk cdti csn att att mixer dzf i2c dit tx cad0 cad1 ttl figure 1. 3-wire serial control mode (i2c = l) ds modulator mcko lrck aoutl pdn dvdd dvss 8x interpolator clock generator lpf ds modulator aoutr 8x interpolator lpf bick sdti serial input interface mcki avdd avss vcom scl sda csn att att mixer dzf i2c dit tx cad0 cad1 ttl figure 2. i 2 c bus control mode (i2c = h)
asahi kasei [AK4353] ms0016-e-01 2000/07 - 3 - n ordering guide AK4353vf -40 ~ +85 c 24pin vsop akd4353 evaluation board n pin layout 6 5 4 3 2 1 mcko tx dvss dvdd mcki bick sdti 7 lrck 8 dzf nc avdd avss vcom aoutl aoutr cad1 top view 10 9 pdn csn scl/cclk 11 sda/cdti 12 cad0 i2c ttl tst 19 20 21 22 23 24 18 17 15 16 14 13
asahi kasei [AK4353] ms0016-e-01 2000/07 - 4 - pin/function no. pin name i/o description 1 mcko o master clock output pin same frequency as mcki is output 2 tx o transmit channel output pin 3 dvdd - digital power supply pin, +2.7 ~ +5.5v 4 dvss - digital ground pin, 0v 5 mcki i master clock input pin 6 bick i serial data clock pin 7 sdti i serial data input pin 8 lrck i serial input channel clock pin 9 pdn i power-down pin when l, the circuit is in power-down mode. the AK4353 should always be reset upon power-up. 10 csn i chip select pin at 3-wire serial control mode this pin should be connected to dvdd at i 2 c bus control mode. scl i control clock pin at i 2 c bus control mode 11 cclk i control clock pin at 3-wire serial control mode sda i/o control data input/output pin at i 2 c bus control mode 12 cdti i control data input pin at 3-wire serial control mode 13 tst i test pin this pin should be connected to dvdd. 14 ttl i digital input level select pin l: cmos, h: ttl 15 i2c i control mode select pin l: 3-wire serial, h: i 2 c bus 16 cad0 i chip address select 0 pin 17 cad1 i chip address select 1 pin 18 aoutr o rch analog output pin 19 aoutl o lch analog output pin 20 vcom o common voltage output pin, avdd/2 used for analog common voltage. large external capacitor is used to reduce power supply noise. 21 avss - analog ground pin 22 avdd - analog power supply pin 23 nc - no connect nothing should be connected externally to this pin. 24 dzf o zero input detect pin when sdti follows a total 8192 lrck cycles with 0 input data or rstn = 0, this pin goes to h. note: no input pins should be left floating.
asahi kasei [AK4353] ms0016-e-01 2000/07 - 5 - absolute maximum ratings (avss, dvss=0v; note 1) parameter symbol min max units power supplies analog digital |avss-dvss| (note 2) avdd dvdd d gnd -0.3 -0.3 - 6.0 6.0 0.3 v v v input current (any pins except for supplies) iin - 10 ma analog input voltage vina -0.3 avdd +0.3 v digital input voltage vind -0.3 dvdd+0.3 v ambient temperature ta -40 85 c storage temperature tstg -65 150 c note:1. all voltages with respect to ground. 2. avss and dvss must be connected to the same analog ground plane. warning: operation at or beyond these limits may results in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, dvss=0v; note 1) parameter symbol min typ max units 3v operation (ttl = l) analog digital avdd dvdd 2.7 2.7 3.0 3.0 5.5 3.6 or avdd v v power supplies (note 3) 5v operation (ttl = h) analog digital avdd dvdd 4.5 4.5 5.0 5.0 5.5 avdd v v note:1. all voltages with respect to ground. 3. the power up sequence between avdd and dvdd is not critical. *akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei [AK4353] ms0016-e-01 2000/07 - 6 - analog characteristics (fs=44.1khz) (ta=25 c; avdd, dvdd=5v; fs=44.1khz; dfs1-0 = 00; cks2-0 = 000; dif2-0 = 101; signal frequency =1khz; measurement frequency=20hz ~ 20khz; unless otherwise specified) parameter min typ max units dynamic characteristics resolution 24 bits s/(n+d) avdd=5v avdd=3v 84 80 90 86 db db dr (-60db input, a-weighted) avdd=5v avdd=3v 94 90 102 97 db db s/n (a-weighted) avdd=5v avdd=3v 94 90 102 97 db db interchannel isolation 90 110 db dc accuracy interchannel gain mismatch 0.2 0.5 db gain drift 20 - ppm/ c output voltage aout=0.6x(avdd-avss) avdd=5v avdd=3v 2.8 1.66 3.0 1.8 3.2 1.94 vpp vpp load resistance (note 4) 10 k w load capacitance 25 pf power supplies power supply current normal operation ( pdn = h) avdd dvdd (note 5) power-down-mode (pdn = l) avdd+dvdd 8 8 10 12 16 100 ma ma m a note:4. ac load. 5. dvdd drops to 4ma at dvdd=3v.
asahi kasei [AK4353] ms0016-e-01 2000/07 - 7 - analog characteristics (fs=96khz) (ta=25 c; avdd, dvdd=5v; fs=96khz; dfs1-0 = 01; cks2-0 = 001; dif2-0 = 101; signal frequency =1khz; measurement frequency=20hz ~ 40khz; unless otherwise specified) parameter min typ max units dynamic characteristics resolution 24 bits s/(n+d) avdd=5v avdd=3v 80 78 86 84 db db dr (-60db input) avdd=5v avdd=3v 88 84 96 92 db db s/n avdd=5v avdd=3v 88 84 96 92 db db interchannel isolation 90 110 db dc accuracy interchannel gain mismatch 0.2 0.5 db gain drift 20 - ppm/ c output voltage aout=0.6x(avdd-avss) avdd=5v avdd=3v 2.8 1.66 3.0 1.8 3.2 1.94 vpp vpp load resistance (note 4) 10 k w load capacitance 25 pf power supplies power supply current normal operation (pdn = h) avdd dvdd (note 6) power-down-mode (pdn = l) avdd+dvdd 8 13 10 12 26 100 ma ma m a note:4. ac load. 6. dvdd drops to 7ma at dvdd=3v.
asahi kasei [AK4353] ms0016-e-01 2000/07 - 8 - filter characteristics (fs=44.1khz) (ta=25 c; avdd, dvdd=2.7 ~ 5.5v; fs=44.1khz; dem=off) parameter symbol min typ max units digital filter passband (note 7) -0.02db -6.0db pb 0 - 22.05 20.0 - khz khz stopband (note 7) sb 24.1 khz pass band ripple pr 0.02 db stopband attenuation sa 54 db group delay (note 8) gd - 20.1 - 1/fs digital filter + analog filter frequency response: 0 ~ 20.0khz fr - 0.2 -db note:7. the passband and stopband frequencies scale with fs. for example, pb=0.4535*fs(@ 0.02db), sb=0.546*fs. 8. the calculating delay time which occurred by digital filtering. this time is from setting the 24bit data of both channels on the input register to the output of analog signal. filter characteristics (fs=96khz) (ta=25 c; avdd, dvdd=2.7 ~ 5.5v; fs=96khz; dem=off) parameter symbol min typ max units digital filter passband (note 7) -0.02db -6.0db pb 0 - 48.0 43.5 - khz khz stopband (note 7) sb 52.5 khz pass band ripple pr 0.02 db stopband attenuation sa 54 db group delay (note 8) gd - 20.1 - 1/fs digital filter + analog filter frequency response: 0 ~ 20.0khz 40.0khz fr - - 0.2 0.2 - - db db note:7. the passband and stopband frequencies scale with fs. for example, pb=0.4535*fs(@ 0.02db), sb=0.546*fs. 8. the calculating delay time which occurred by digital filtering. this time is from setting the 24bit data of both channels on the input register to the output of analog signal.
asahi kasei [AK4353] ms0016-e-01 2000/07 - 9 - digital characteristics (cmos level input) (ta=25 c; avdd=2.7 ~ 5.5v; dvdd=2.7 ~ 3.6v; ttl = l) parameter symbol min typ max units high-l evel i nput voltage low-level i nput voltage vih vil 0.7xdvdd - - - - 0.3xdvdd v v high-l evel o utput voltage (tx, mcko pins: iout=-100a) (dzf pin: iout=-100a) low-level o utput voltage (tx, mcko, dzf pins: iout= 100a) (sda pin: iout= 3ma) voh voh vol vol dvdd-0.5 avdd-0.5 - - - - - - - - 0.5 0.4 v v v v input leakage c urrent iin - - 10 m a digital characteristics (ttl level input; except for ttl pin) (ta=25 c; avdd, dvdd=4.5 ~ 5.5v; ttl = h) parameter symbol min typ max units high-l evel i nput voltage (ttl pin) (all pins except for ttl pin) low-level i nput voltage (ttl pin) (all pins except for ttl pin) vih vih vil vil 0.7xdvdd 2.2 - - - - - - - - 0.3xdvdd 0.8 v v v v high-l evel o utput voltage (tx, mcko pins: iout=-100a) (dzf pin: iout=-100a) low-level o utput voltage (tx, mcko, dzf pins: iout= 100a) (sda pin: iout= 3ma) voh voh vol vol dvdd-0.5 avdd-0.5 - - - - - - - - 0.5 0.4 v v v v input leakage c urrent iin - - 10 m a
asahi kasei [AK4353] ms0016-e-01 2000/07 - 10 - switching characteristics (ta=25 c; avdd, dvdd=2.7 ~ 5.5v; c l =20pf) parameter symbol min typ max units master clock input: frequency 128fs/256fs/512fs/1024fs 192fs/384fs/768fs/1536fs duty cycle fclk fclk dclk 4.096 6.144 40 24.576 36.864 60 mhz mhz % lrck: (note 9) frequency half speed mode (dfs1-0 = 11) normal speed mode (dfs1-0 = 00) double speed mode (dfs1-0 = 01) duty cycle fsh fsn fsd duty 16 32 64 45 24 48 96 55 khz khz khz % serial interface timing: bick period half speed mode normal speed mode double speed mode bick pulse width low bick pulse width high bick - to lrck edge (note 10) lrck edge to bick - (note 10) sdti hold time sdti setup time tbck tbck tbck tbckl tbckh tblr tlrb tsdh tsds 1/128fs 1/128fs 1/64fs 70 70 40 40 40 40 ns ns ns ns ns ns ns ns ns power-down & reset timing pdn pulse width (note 11) tpdw 150 ns note: 9. if sampling speed mode (dfs0-1) changes, please reset by pdn pin or rstn bit. 10. bick rising edge must not occur at the same time as lrck edge. 11. the AK4353 can be reset by pdn pin l upon power up. if cks0-2 or dfs0-1 changes, the AK4353 should be reset by pdn pin or rstn bit.
asahi kasei [AK4353] ms0016-e-01 2000/07 - 11 - parameter symbol min typ max units control interface timing (3-wire serial mode): cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn h time csn to cclk - cclk - to csn - tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 40 40 150 50 50 ns ns ns ns ns ns ns ns control interface timing (i 2 c bus mode): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling (note 12) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp - 4.7 4.0 4.7 4.0 4.7 0 0.25 - - 4.0 0 100 - - - - - - - 1.0 0.3 - 50 khz m s m s m s m s m s m s m s m s m s m s ns note:12. data must be held for sufficient time to bridge the 300 ns transition time of scl.
asahi kasei [AK4353] ms0016-e-01 2000/07 - 12 - n timing diagram 1/fclk tclkl vih tclkh mcki vil dclk=tclkh*fclk*100 =tclkl*fclk*100 vih lrck vil 1/fs 1/fbck tbckl vih tbckh bick vil clock timing tlrb lrck vih bick vil tsds vih sdti vil tsdh vih vil tblr serial interface timing tpdw vil pdn power-down & reset timing
asahi kasei [AK4353] ms0016-e-01 2000/07 - 13 - tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh write command input timing (3-wire serial mode) csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh write data input timing (3-wire serial mode) thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp i 2 c bus mode timing
asahi kasei [AK4353] ms0016-e-01 2000/07 - 14 - operation overview n system clock input the external clocks which are required to operate the AK4353 are mcki, lrck and bick. the master clock (mcki) should be synchronized with sampling clock (lrck) but the phase is not critical. mcki is used to operate the digital interpolation filter and the delta-sigma modulator. the frequency of mcki can be set by cks2-0, and can be selected to half, normal or double speed mode by dfs1-0 (see table 1). all external clocks (mcki,bick,lrck) should always be present whenever the AK4353 is in the normal operation mode (pdn = h). if these clock are not provided, the AK4353 may draw excess current and may not possibly operate properly because the device utilizes dynamic refreshed logic internally. if the external clocks are not present, the AK4353 should be in the power-down mode (pdn = l) or in the reset mode (rstn = 0). after exiting reset at power-up etc., the AK4353 is in the power-down mode until mcki and lrck are input. when the register data of cks2-0 or dfs1-0 is changed during normal operation, the AK4353 should be reset by pdn pin l or rstn bit 0. dfs1-0 cks2 cks1 cks0 11 (half speed) 00 (normal speed) 01 (double speed) 0 0 0 512fs 256fs 128fs default (dfs1-0 = 00) 0 0 1 256fs 256fs 256fs 0 1 0 768fs 384fs 192fs 0 1 1 384fs 384fs 384fs 1 0 0 1024fs 512fs 256fs 1 0 1 512fs 512fs n/a 1 1 0 1536fs 768fs 384fs 1 1 1 768fs 768fs n/a table 1. system clock (dfs1-0=10: reserved) fs [khz] mode 128fs 192fs 256fs 384fs 512fs 768fs 1024fs 1536fs 16 32 64 half normal double - - 8.1920 - - 12.2880 4.0960 8.1920 16.3840 6.1440 12.2880 24.5760 8.1920 16.3840 - 12.2880 24.5760 - 16.3840 - - 24.5760 - - 22.05 44.1 88.2 half normal double - - 11.2896 - - 16.9344 5.6448 11.2896 22.5792 8.4672 16.9344 33.8688 11.2896 22.5792 - 16.9344 33.8688 - 22.5792 - - 33.8688 - - 24 48 96 half normal double - - 12.2880 - - 18.4320 6.1440 12.2880 24.5760 9.2160 18.4320 36.8640 12.2880 24.5760 - 18.4320 36.8640 - 24.5760 - - 36.8640 - - table 2. example of system clock [mhz]
asahi kasei [AK4353] ms0016-e-01 2000/07 - 15 - n audio serial interface format data is shifted in via the sdti pin using bick and lrck inputs. 6 serial data modes are supported and selected by register data of dif2-0 as shown in table 3. in all modes the serial data is msb-first, 2s compliment format and is latched on the rising edge of bick. mode 4 can be used for 20, 18 and 16 msb justified formats by zeroing the unused lsbs. mode dif2 dif1 dif0 sdti l/r bick 0 0 0 0 16bit, lsb justified h/l 3 32fs 1 0 0 1 18bit, lsb justified h/l 3 36fs 2 0 1 0 20bit, lsb justified h/l 3 40fs 3 0 1 1 24bit, lsb justified h/l 3 48fs 4 1 0 0 24bit, msb justified h/l 3 48fs 5101 i 2 s l/h 3 48fs default 6 1 1 0 reserved 7 1 1 1 reserved table 3. audio data format sdti bick lrck sdti 15 14 6 5 4 bick 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 3 2 1 0 15 14 (32fs) (64fs) 014 1 15 16 17 31 0 1 14 15 16 17 31 0 1 15 14 0 15 14 0 mode 0 dont care dont care 15:msb, 0:lsb mode 0 sdti mode 1 17:msb, 0:lsb sdti bick (64fs) mode 2 sdti mode 3 15 14 6 5 4 3 2 1 0 15 14 0 15 14 0 dont care dont care 17 16 17 16 08 1 711123101 8 711123101 19 0 19 0 dont care dont care 19:msb, 0:lsb 23:msb, 0:lsb 20 19 0 20 19 0 dont care dont care 23 23 lch data rch data figure 3. mode 0-3 timing
asahi kasei [AK4353] ms0016-e-01 2000/07 - 16 - lrck bick (64fs) sdti 022 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 dont care 23 lch data rch data 23 30 22 224 23 30 22 1 0 dont care 23 22 23 fig ure 4. mode 4 timing lrck bick (64fs) sdti 03 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 dont care 23 lch data rch data 23 25 3 224 23 25 22 1 0 dont care 23 bick (32fs) sdti 03 1 2 12 15 0 1 0 1 23 22 13 8 11 14 2 12 11 10 9 13 3 12 15 11 14 13 23 22 13 8 12 11 10 9 23 8 23 figure 5. mode 5 timing n data transmission format data input via sdti pin is formatted in digital interface format and output via tx pin. data transmitted on the tx output is formatted in blocks as shown in figure 6. each block consists of 192 frames. a frame of data contains two sub-frames. a sub-frame consists of 32 bits of information. each data bit received is coded using a bi-phase mark encoding as a two binary state symbol. the preambles violate bi-phase encoding so they may be differentiated from data. in bi-phase encoding, the first state of an input symbol is always the inverse of the last state of the previous data symbol. for a logic 0, the second state of the symbol is the same as the first state. for a 1, the second state is the opposite of the first. figur e 7 illustrates a sample stream of 8 data bits encoded in 16 symbol states. frame 191 frame 0 frame 1 sub-frame sub-frame m channel 1 w channel 2 b channel 1 w channel 2 m channel 1 w channel 2 figure 6. block format
asahi kasei [AK4353] ms0016-e-01 2000/07 - 17 - 0 11 0 0 00 1 figure 7. a biphase-encoded bit stream the sub-frame is defined in the figure below: - bits 0-3 of the sub-frame represent a preamble for synchronization. there are three preambles: the block preamble, b, is contained in the first sub-frame of frame 0. the channel 1 preamble, m, is contained in the first sub-frame of all other frames. the channel 2 preamble, w, is contained in all of the second sub-frames. table 4 defines the symbol encoding for each of the preambles. - bits 4-27 of the sub-frame contain the 24 bit audio sample in 2s complement format with bit 27 as the most significant bit (msb). for 16 bit mode, bits 4-11 are all 0. - bit 28 is the validity flag. this is equal to v bit in the register. - bit 29 is a user data bit. this is always 0 in the AK4353. - bit 30 is a channel status bit. frame 0 contains the first bit of the 192 bit word with the last bit in frame 191. - bit 31 is an even parity bit for bits 4-31 of the sub-frame. sync p c u v l m s audio sample s b b 0 3 4 27 28 29 30 31 figure 8. sub-frame format the block of data contains consecutive frames transmitted at a bit rate of 64 times the sample frequency, fs. preamble preceding state = 0 preceding state = 1 b 11101000 00010111 m 11100010 00011101 w 11100100 00011011 table 4. sub-frame preamble encoding figure 9 shows the relation between input data to sdti pin and audio data on sub-frame. l m s audio sample s b b 4 27 0 15 0 17 0 19 0 23 mode 0 mode 1 mode 2 mode 3,4,5 1 2 3 4 5 6 7 8 1 2 3 4 1 2 sub-frame figure 9. relation between input data to sdti pin and audio data on sub-frame
asahi kasei [AK4353] ms0016-e-01 2000/07 - 18 - n de-emphasis filter a digital de-emphasis filter is available for 32, 44.1 or 48khz sampling speed (tc=50/15 m s). it is enabled or disabled with the control register data of dem1-0 and dfs1-0. the de-emphasis filter is disabled at half/double sampling mode. dem1 dem0 de-emphasis 0 0 44.1khz 0 1 off default 1 0 48khz 1 1 32khz table 5. de-emphasis filter control with dem1-0 (dfs1-0=00) dfs1 dfs0 de-emphasis 0 0 see table 5. default 0 1 off 1 0 off 1 1 off table 6. de-emphasis filter control with dfs1-0
asahi kasei [AK4353] ms0016-e-01 2000/07 - 19 - n zero detection when the input data at both channels is continuously zeros for 8192 lrck cycles, dzf pin goes to h. dzf pin immediately goes to l if input data is not zero after going dzf h. if rstn bit becomes 0, dzf pin goes to h. dzf pin goes to l at 4 ~ 5/fs after rstn bit returns to 1. n soft mute operation soft mute operation is performed at digital domain. when the serial control register data of smute goes 1, the output signal is attenuated by - during 1024 lrck cycles. when smute is returned to 0, the mute is cancelled and the output attenuation gradually changes to 0db during 1024 lrck cycles. if the soft mute is cancelled within 1024 lrck cycles after starting the operation, the attenuation is discontinued and returned to 0db. the soft mute is effective for changing the signal source without stopping the signal transmission. smute bit attenuation dzf pin 1024/fs 0db - aout 1024/fs 8192/fs gd gd (1) (2) (3) (4) notes: (1) the output signal is attenuated by - during 1024 lrck cycles (1024/fs). (2) analog output corresponding to digital input have the group delay (gd). (3) if the soft mute is cancelled within 1024 lrck cycles, the attenuation is discontinued and returned to 0db. (4) when the input data at both channels are continuously zeros for 8192 lrck cycles, dzf pin goes to h. dzf pin immediately goes to l if input data are not zero after going dzf h. figure 10. soft mute and zero detection
asahi kasei [AK4353] ms0016-e-01 2000/07 - 20 - n power-down the dac is placed in the power-down mode by bringing pdn pin l and the digital filter is also reset at the same time. the internal register values are initialized by pdn l. this reset should always be done after power-up. because some click noise occurs at the edge of pdn, the analog output should be muted externally if the click noise influences system application. normal operation internal state pdn power-down normal operation gd gd 0 data d/a out (analog) d/a in (digital) clock in mcki, lrck, bick (1) (3) (6) dzf external mute (5) (3) (1) mute on (2) (4) dont care notes: (1) the analog output corresponding to digital input has the group delay (gd). (2) analog outputs are floating (hi -z) at the power-down mode. (3) click noise occurs at the edge of pdn signal. this noise is output even if 0 data is input. (4) the external clocks (mcki, bick and lrck) can be stopped in the power-down mode (pdn = l). (5) please mute the analog output externally if the click noise (3) influences system application. the timing example is shown in this figure. (6) dzf pin is l in the power-down mode (pdn = l). figure 11. power-down/up sequence example
asahi kasei [AK4353] ms0016-e-01 2000/07 - 21 - n reset function when rstn = 0, the dac is powered down but the internal register values are not initialized. the analog outputs go to vcom voltage and dzf pin goes to h. figure 12 shows the sequence of reset by rstn bit. internal state rstn bit digital block power-down normal operation gd gd 0 data d/a out (analog) d/a in (digital) clock in mcki,lrck,bick (1) (3) dzf (3) (1) (2) normal operation 2/fs(5) internal rstn bit 2~3/fs (6) dont care (4) notes: (1) the analog output corresponding to digital input has the group delay (gd). (2) analog outputs go to vcom voltage. (3) click noise occurs at the edges( - ) of the internal timing of rstn bit. this noise is output even if 0 data is input. (4) the external clocks (mcki, bick and lrck) can be stopped in the reset mode (rstn = l). (5) dzf pin goes to h when the rstn bit becomes 0, and goes to l at 4~ 5/fs after rstn bit becomes 1. (6) there is a delay, 2~3/fs from rstn bit 1 to the internal rstn 1. figure 12. reset sequence example
asahi kasei [AK4353] ms0016-e-01 2000/07 - 22 - n serial control interface the AK4353 can control its functions via registers. internal registers may be written by 2 types of control mode. the chip address is determined by the state of the cad0 and cad1 inputs. pdn = l initializes the registers to their default values. writing 0 to the rstn bit can initialize the internal timing circuit. but in this case, the register data is not be initialized. (1) 3-wire serial control mode (i2c = l) internal registers may be written to the 3 wire p interface pins (csn,cclk and cdti). the data on this interface consists of chip address (2bits, cad0/1), read/write (1bit, fixed to 1; write only), register address (msb first, 5bits) and control data (msb first, 8bits). address and data is clocked in on the rising edge of cclk and data is clocked out on the falling edge. for write operations, data is latched after a low-to-high transition of csn. the clock speed of cclk is 5mhz(max). the csn and cclk pins should be held to h except for access. cdti cclk csn c1 0 1234567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 c1-c0: chip address (c1=cad1, c0=cad0) r/w: read/write (fixed to 1 : write only) a4-a0: register address d7-d0: control data (2) i 2 c bus control mode (i2c = h) internal registers may be written to i 2 c bus interface pins: scl & sda. the data on this interface consists of chip address (2bits, cad0/1), read/write (1bit, fixed to 0; write only), register address (msb first, 5bits) and control data (msb first, 8bits). address and data is clocked in on the rising edge of scl and data is clocked out on the falling edge. data can be written after a high-to-low transition of sda when scl is h(start condition), and is latched after a low-to-high transition of sda when scl is h(stop condition). the clock speed of scl is 100khz(max). the csn pin should be connected to dvdd at i 2 c bus control mode. the AK4353 does not have a register address auto increment capability. scl sda 0 0100 r/w start stop ack ack ack c1 c0 0 0 0 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 c1-c0: chip address (c1=cad1, c0=cad0) r/w: read/write (fixed to 0 : write only) a4-a0: register address d7-d0: control data ack: acknowledge * when the AK4353 is in the power down mode (pdn = l) or the mclk is not provided, writing into the control register is inhibited.
asahi kasei [AK4353] ms0016-e-01 2000/07 - 23 - n mapping of program registers addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 0 0 0 0 dif2 dif1 dif0 rstn 01h control 2 0 0 dfs1 dfs0 cks2 cks1 cks0 rstn 02h control 3 pl3 pl2 pl1 pl0 dem1 dem0 atc smute 03h lch att att7 att6 att5 att4 att3 att2 att1 att0 04h rch att att7 att6 att5 att4 att3 att2 att1 att0 05htx 000000vtxe 06h channel status 1 0 cs29 cs28 cs25 cs24 cs3 cs2 cs1 07h channel status 2 cs15 cs14 cs13 cs12 cs11 cs10 cs9 cs8 note: for addresses from 08h to 1fh, data should not be written. when pdn goes to l, the registers are initialized to their default values. when rstn bit goes to 0, the internal timing is reset, dzf pin goes to h and registers are not initialized to their default values.
asahi kasei [AK4353] ms0016-e-01 2000/07 - 24 - n register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 0 0 0 0 dif2 dif1 dif0 rstn default 0 0 0 0 1 0 1 1 rstn: internal timing reset 0: reset. dzf pin goes to h and registers are not initialized. 1: normal operation when the states of dif2-0,cks2-0 or dfs1-0 changes, the AK4353 should be reset by pdn pin or rstn bit. some click noise may occur at that timing. dif2-0: audio data interface modes (see table 3.) initial: 101, mode 5 addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 0 0 dfs1 dfs0 cks2 cks1 cks0 rstn default 0 0 0 0 0 0 0 1 rstn: internal timing reset 0: reset. dzf pin goes to h and registers are not initialized. 1: normal operation when the states of dif2-0,cks2-0 or dfs1-0 changes, the AK4353 should be reset by pdn pin or rstn bit. some click noise may occur at that timing. cks2-0: clock select (see table 1.) initial: 000 dfs1-0: half/normal/double sampling modes (see table 1), de-emphasis response (see table 6.) initial: 00
asahi kasei [AK4353] ms0016-e-01 2000/07 - 25 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h control 3 pl3 pl2 pl1 pl0 dem1 dem0 atc smute default 1 0 0 1 0 1 0 0 smute: soft mute enable 0: normal operation 1: dac outputs soft-muted atc: attenuation control 0: the attenuation data for each register is applied separately to left and right channels. 1: the attenuation data loaded in addr=03h is used for both left and right channels. dem1-0: de-emphases response (see table 5,6.) initial: 01, off pl3-0: mixing mode pl3 pl2 pl1 pl0 lch output rch output note 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 mute mute mute mute mute r l (l+r)/2 mute 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 r r r r mute r l (l+r)/2 reverse 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 l l l l mute r l (l+r)/2 stereo default 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 (l+r)/2 (l+r)/2 (l+r)/2 (l+r)/2 mute r l (l+r)/2 mono table 7. programmable output format stereo: normal stereo output reverse: l/r reverse output mono: monaural output mute: soft mute operation
asahi kasei [AK4353] ms0016-e-01 2000/07 - 26 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h lch att att7 att6 att5 att4 att3 att2 att1 att0 04h rch att att7 att6 att5 att4 att3 att2 att1 att0 default 1 1 1 1 1 1 1 1 equation of attenuation level: att = 20 x log 10 (binary level / 255) [db] ffh: 0db : 01h: -48.1db 00h: mute the transition between att values is same as soft mute operation. when current value is att1 and new value is set as att2, att1 gradually becomes att2 with same operation as soft mute. if new value is set as att3 before reaching att2, att value gradually becomes att3 from the way of transition. cycle time of soft mute: ts=1024/fs when pdn pin goes to l, the att values are set to 00h. the att values fade to ffh(0db) during ts after pdn pin returns to h. when rstn bit goes to 0, the att values are set to 00h. the att values fade to their current values after rstn bit returns to 1. digital attenuator is independent of soft mute function.
asahi kasei [AK4353] ms0016-e-01 2000/07 - 27 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 05htx 000000vtxe default 0 0 0 0 0 0 0 1 txe: tx output 0: l 1: normal operation v: validity flag 0: valid 1: invalid addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h channel status 1 0 cs29 cs28 cs25 cs24 cs3 cs2 cs1 default 0 0 0 0 0 0 0 0 cs1 0: audio 1: non-audio cs2 0: copyright 1: non-copyright cs3 0: no pre-emphasis 1: 50/15sec pre-emphasis cs24,25: sampling frequency 00: 44.1khz 01: 48khz 10: reserved 11: 32khz cs28,29: clock accuracy 00: standard mode 01: variable pitch mode 10: high accuracy mode 11: reserved addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h channel status 2 cs15 cs14 cs13 cs12 cs11 cs10 cs9 cs8 default 0 0 0 0 0 1 0 0 cs8-15: category code (see the standard of eiaj.) 00100000: digital audio broadcast reception in japan (default)
asahi kasei [AK4353] ms0016-e-01 2000/07 - 28 - n channel status explanation (from the standard of eiaj and iec958) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte 0 cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 byte 1 cs15 cs14 cs13 cs12 cs11 cs10 cs9 cs8 byte 2 cs23 cs22 cs21 cs20 cs19 cs18 cs17 cs16 byte 3 cs31 cs30 cs29 cs28 cs27 cs26 cs25 cs24 (bold type: programmable, normal type: fixed in this device) cs0 0: consumer (fixed) cs1 0: audio 1: non-audio cs2 0: copyright 1: non-copyright cs3 -5 000: no pre-emphasis 100: 50/15sec pre-emphasis (cs4-5: fixed to 00) cs6-7: mode 00: mode 0 (fixed) cs8-15 : category code (see the next page. for more detail information, please see the standard of eiaj.) cs16-19: source number 00: not regulated (fixed) cs20-23: channel (fixed) 1000: left 0100: right cs24 -27: sampling frequency 0000: 44.1khz 0100: 48khz 1100: 32khz others: not regulated cs28-29 : clock accuracy 00: standard mode 01: variable pitch mode 10: high accuracy mode 11: not regulated cs30- : reserved (fixed to all 0)
asahi kasei [AK4353] ms0016-e-01 2000/07 - 29 - category code (bit 8-15) bit15 (l bit): indicates generation of digital audio signal. general 0: not regulated 1: recorded software issued for business optical disc machine (100 xxxxl), broadcast reception (001 xxxxl and 011 1xxxl) 0: recorded software issued for business 1: not regulated 000 00000: general (digital audio reception without copyright information in japan) 100 xxxxl:optical disc machine 100 0000l:compact disc adapted to iec908 100 1000l:optical disc not adapted to iec908 100 1001l:mini disc system 100 1100l:digital video disc 010 xxxxl and 011 1xxxl: digital/digital converting machine and signal process machine 010 0000l:pcm encoder/decoder 010 0100l:digital signal mixer 010 1100l:sampling rate converter 010 0010l:digital sound sampler 110 xxxxl:magnetic tape and magnetic disc machine 110 0000l:digital audio tape 110 1000l:video tape recorder with digital voice 110 0001l:digital compact cassette 001 xxxxl:digital audio broadcast reception 001 0000l:in japan (001 00000: default) 001 1000l:in europe 001 0011l:in u.s.a 001 0001l:software electronics delivery 101 xxxxl: music instrument, microphone and source processing original signal 101 0000l:synthesizer 101 1000l:microphone 011 00xxx: a/d converter without copyright information 011 0000x: a/d converter 011 01xxl: a/d con verter with copyright information 011 0100l:a/d converter 000 1xxxl:solid memory machine 000 0001l:experimental machine not used for business 111 xxxxl:not regulated 000 0xxxl:not regulated (except for 000 00000 and 000 0001l)
asahi kasei [AK4353] ms0016-e-01 2000/07 - 30 - system design figure 13 shows the system connection diagram. an evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. condition: avdd=dvdd=5v(ttl mode), i2c mode, chip address=00 mcko 1 tx 2 dvdd 3 dvss 4 mcki 5 bick 6 sdti 7 lrck 8 pdn 9 csn 10 scl 11 sda 12 dzf 24 nc 23 avdd 22 avss 21 vcom 20 aoutl 19 aoutr 18 cad1 17 cad0 16 i2c 15 ttl 14 tst 13 optical clock decoder up reset 0.1u 10u + 10u 0.1u + 10u 27k 220 10u 27k 220 10u + rch mute lch mute 5 analog 5v system ground analog ground AK4353 top view lch out rch out 0.1u + + external figure 13. typical connection diagram
asahi kasei [AK4353] ms0016-e-01 2000/07 - 31 - analog ground digital ground system controller mcko 1 tx 2 dvdd 3 dvss 4 mcki 5 bick 6 sdti 7 lrck 8 pdn 9 csn 10 scl 11 sda 12 dzf 24 nc 23 avdd 22 avss 21 vcom 20 aoutl 19 aoutr 18 cad1 17 cad0 16 i2c 15 ttl 14 tst 13 AK4353 figure 14. ground layout note: avss and dvss must be connected to the same analog ground plane. 1. grounding and power supply decoupling the AK4353 requires careful attention to power supply and grounding arrangements. avdd and dvdd are usually supplied from analog supply in system. alternatively if avdd and dvdd are supplied separately, the power up sequence is not critical. avss and dvss of the AK4353 must be connected to analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be near to the AK4353 as possible, with the small value ceramic capacitors being the nearest. 2. voltage reference inputs the differential voltage between avdd and avss sets the analog output range. vcom is avdd/2 and normally connected to avdd with a 0.1 m f ceramic capacitor. an electrolytic capacitor 10 m f parallel with a 0.1 m f ceramic capacitor attached to vcom pin eliminates the effects of high frequency noise. no load current may be drawn from these pins. all signals, especially clocks, should be kept away from the vcom pin in order to avoid unwanted coupling into the AK4353. 3. analog outputs the analog outputs are single-ended outputs and 0.6x(avdd-avss) vpp ( typ) centered around the vcom voltage. the internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. the input data format is 2s complement. the output voltage is a positive full scale for 7fffff(@24bit) and a negative full scale for 800000h(@24bit). the ideal output is 0v for 000000h(@24bit).
asahi kasei [AK4353] ms0016-e-01 2000/07 - 32 - package 0.1 0.1 0-10 detail a seating plane note: dimension "*" does not include mold flash. 0.10 0.15 0.05 0.22 0.1 0.65 *7.8 0.15 1.25 0.2 a 1 12 13 24 24pin vsop ( unit: mm ) 7.6 0.2 0.5 0.2 *5.6 0.2 n package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder plate
asahi kasei [AK4353] ms0016-e-01 2000/07 - 33 - marking akm AK4353vf aaxxxx contents of aaxxxx aa: lot# xxxx: date code important notice these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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